A memory cell of a semiconductor DRAM typically consists of a storage capacitor and an access transistor. One terminal of the capacitor is connected to the source or the drain of the transistor. The other terminal and the gate electrode of the transistor are connected to external connection lines, which are known as the bit line and the word line, respectively. The other terminal of the capacitor is connected to a reference voltage. Thus, the formation of a DRAM cell comprises the formation of a transistor, the formation of a capacitor, the formation of the contacts to the capacitor and the formation of the connection lines.
In recent years, the development of the semiconductor memory device become highly integrated and highly packing density, the area occupied by a capacitor of a DRAM storage cell shrinks, thus decreasing the capacitance of the capacitor owing to its smaller electrode surface area. However, a relatively large capacitance is required to achieve a high signal-to-noise radiation in reading the memory cell and to reduce soft errors (due to alpha particle interference). Therefore, it is desirable to reduce the cell dimension and yet obtain a high capacitance, which achieves both high cell integration and reliable operation.
The capacitor type that is most typically used in DRAM memory cells is planar capacitor, which is relatively simple to manufacture. For very small memory cells, planar capacitor becomes very difficult to use reliably. One approach for increasing the capacitance while maintaining the high integration of the memory cells is directed toward the shape of the capacitor electrodes. In this approach, the polysilicon layer implementing the capacitor electrodes may have protrusions, cavities, fins, etc., to increasing the surface area of the capacitor electrode, so that increases its capacitance while maintaining the small area occupied on the substrate surface. In addition, capacitors with hemispherical-grain (HSG) polysilicon storage nodes and crown structure have been used in the manufacture of DRAM. The HSG polysilicon storage node increases the surface area of the capacitor, so that increases the capacitance. Increasing the height of stacked cells can also increase the capacitance of a stacked capacitor without increasing the planar area of the capacitor. Reducing the thickness of the dielectric also can improve the capacitance of the capacitor, but this approach is limited because of yield and reliability problems.
A capacitor-over-bit-line (COB) cell with a hemispherical-grain (HSG) polysilicon storage node has been developed (see "A CAPACITOR-OVER-BIT-LINE (COB) CELL WITH A HEMISPHERICAL-GRAIN STORGE NODE FOR 64 Mb DRAMs", M. Sakao etc. microelectronics research laboratories, NEC Corporation). The HSG--Si is deposited by low-pressure chemical vapor deposition method at the transition temperature from amorphous-Si to polycrystalline-Si. Further, a cylindrical capacitor using hemispherical-grained Si have been proposed (see "A NEW CYLIDRICAL CAPACITOR USING HEMISPHERICAL GRAINED Si (HSG--Si) FOR 256 Mb DRAMs", H. Watanabe et al., Tech Dig, December 1992, pp. 259-262).
When the dimension of DRAM is close to deep-submicron, a new method for manufacturing small capacitors is needed. A method to fabricate a multiple fin-pillar capacitor using a hemispherical-grained silicon is needed.